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genesys logic, inc. GL800USB - usb2.0 utmi compliant t r ansceiver specification 1.1 a ugust 02, 2001 genesy s logic, inc. 10f , no.1 1, ln.3, t s ao t i w e i, shenkeng, t a ipei, t a iwan t e l: 886-2-2664-6655 fax: 886-2-2664-5757 htt p ://www . g enes y slo g ic.com
gl 80 0 u sb - usb 2 . 0 utm i com p l i a n t tra n sce i v e r content s 1. general d escription ......................................................................................... 3 2. feat ures ............................................................................................................ 4 3. sy stem conf iguration ...................................................................................... 5 3.1 system diagram ........................................................................................... 5 3.2 system de scription ....................................................................................... 5 4. function block ................................................................................................. 6 4.1 block diagram .............................................................................................. 6 4.2 functional overview ..................................................................................... 7 5. pinning in formatio n ......................................................................................... 9 5.1 pin assi gnm ent ............................................................................................. 9 5.2 pin descr iption ........................................................................................... 10 6. functional d escripti on .................................................................................. 14 6.1 t r ansm i t o peratio n ..................................................................................... 14 6.2 receive o peratio n ...................................................................................... 15 7. electric a l ch aracteris tics .............................................................................. 18 7.1 absolute ma xim u m ra tings ........................................................................ 18 7.2 dc characteristics (digit al pins) ................................................................ 18 7.3 dc characterist ics (d+/ d-) ......................................................................... 19 7.4 switching char acterist ics ........................................................................... 19 7.5 t i m i ng chart ............................................................................................... 20 8. package di mension ....................................................................................... 22 9. revision history ............................................................................................. 23 ?2 00 0 - 2 0 0 1 g e nesy s l o gi c i n c.? a l l ri ght s rese rve d . page 2 of 23
gl 80 0 u sb - usb 2 . 0 utm i com p l i a n t tra n sce i v e r 1. general description GL800USB is a high performance usb 2.0 t r ansceiver compliant with the utmi (usb 2.0 t r ansceiver macrocell interface) s pecification proposed by intel. the utmi specification defines a st andard interface to usb 2.0 high-speed transceivers that enables common design across prototype and production implement ations. the GL800USB integrates high-speed, mixed-signal circuitry to serve as the interface between the high performance usb serial bus and the 16-bit sie bus. the transceiver is controlled by input signals from the sie bus, which is synchronized with the 30mhz clock output. the utmi transceiver handles the low level usb protocol and signaling. this includes features such as: dat a serialization and deserialization, bit stuf fing and clock recovery and synchronization. the primary focus of the utmi transceiver is to shif t the clock domain of the dat a from the usb 2.0 rate to one that is comp atible with the general logic. t o eliminate the dif f icult high-speed, mixed-signal usb 2.0 logic design for system and peripheral developers, the GL800USB with st andard utmi and 40x improvement in dat a rate can be easily adapted for implement ation of usb 2.0 high speed compliant design of widely applications, including scanners, printers, port able storage, external cd-rom / cd-r w / dvd-rom, flash card readers, and pc cameras. ?2 00 0 - 2 0 0 1 g e nesy s l o gi c i n c.? a l l ri ght s rese rve d . page 3 of 23
gl 80 0 u sb - usb 2 . 0 utm i com p l i a n t tra n sce i v e r 2. features
gl 80 0 u sb - usb 2 . 0 utm i com p l i a n t tra n sce i v e r 3. sy stem configuration 3.1 sy stem diagram GL800USB sie (serial interface engine) device s pecific logic utmi usb 2.0 t r ansceiver macrocell interface usb 2.0 3.2 sy stem description 3.2.1 GL800USB the usb 2.0 utmi t r ansceiver , which handles the low level usb protocol and signaling, and shif t s the clock domain of the dat a from the usb 2.0 rate to one that is comp atible with the general logic. 3.2.2 serial interface engine the serial interface engine can be further sub-divided into 2 types of sub-blocks; the sie control logic and the end point logic. the sie control logic cont ains the usb pid and address recognition logic, and other sequencing and st ate machine logic to handle usb p a cket s and transactions. the end point logic cont ains the end point specific logic: end point number recognition, fifos and fifo control, etc. sie logic module can be developed by peri pheral vendors or purchased from ip vendors. the st andardization of the utmi allows multiple sources of sie logic to connect with GL800USB to implement the usb 2.0 high-s peed design. 3.2.3 device specific logic this block is the glue that ties the usb interface to the specific application of the device. ?2 00 0 - 2 0 0 1 g e nesy s l o gi c i n c.? a l l ri ght s rese rve d . page 5 of 23
gl 80 0 u sb - usb 2 . 0 utm i com p l i a n t tra n sce i v e r 4. function block 4.1 block diagram hs xcvr fs xcvr hs dll elasticity buf f er m u x nrzi decoder bit unstuf fer rx register parallel rx dat a receive s t ate machine t r ansmit s t ate machine tx register parallel tx dat a bit st u f f e r nrzi encoder fs dll & dat a recovery external cryst a l clock multiplier control logic control clk s t atus/ control xmi t rcv s t atus/ control xmi t rcv dat a + dat a - analog front end ?2 00 0 - 2 0 0 1 g e nesy s l o gi c i n c.? a l l ri ght s rese rve d . page 6 of 23
gl 80 0 u sb - usb 2 . 0 utm i com p l i a n t tra n sce i v e r 4.2 functional overview 4.2.1 hs xcvr hs xcvr c ontains the low-level analog circu i tr y required t o physically interface usb 2.0 signaling to the usb dp/dm signal lines. 4.2.2 fs xcvr fs x c vr includes the logic necessary to send and receive the fs data on usb. 4.2.3 clock multiplier clock multiplier gener ates the in ternal clocks for the GL800USB usb 2 . 0 transceiver and the clkout sig nal. all data transfer signals are synchronized with the clkout signal. in hs mode there is one clock cycle per byte time. the frequency of clock does not change when the utmi is switched between hs to fs mod e s. in fs mode there are 5 clock cycles per fs bit time, t y pically 40 clock cycle s per fs b y t e time. if a received byte contains a stuffed bit t hen the byte boundary can be stret c hed to 45 clock cycles, and two stuffed bits would re sult in a 50 clock delay between bytes. 4.2.4 hs dll (high speed delay line pll) dll extracts clo ck and data from the data received over th e usb 2.0 interface for reception b y the rec e ive deserializer. the data output from th e dll is synchronous with the local clock. 4.2.5 elasticity buffer elasticity buffer is use d to compe n sate for difference bet ween transmitting and receiv ing cl ocks. th e usb specifi c a t ion define s a m a x i m u m cloc k error of +/- 500 ppm. when the error is calcula t ed over the maxi mum packet size up to +/- 12 bits of drift can occur. the elasticity bu ffer is f illed to a thresho l d prior to e nabling the remainder of the down stream receive logic. overview an d underflow condition s detected in th e elasticity buffer can be reported with the rxerr signal. 4.2.6 mux the mux bl ock allows t he data from the hs o r fs receivers to be ro uted to the shared receive logic. the state of the mux is determined by the fspeed input. 4.2.7 nrzi decoder the nrzi decoder is compliant to standard usb 1. x s pecification, and it can operate at fs and hs data rates. ?2 00 0 - 2 0 0 1 g e nesy s l o gi c i n c.? a l l ri ght s rese rve d . page 7 of 23
gl 80 0 u sb - usb 2 . 0 utm i com p l i a n t tra n sce i v e r 4.2.8 bit unstuffer the bit un stuffer is compliant to standard usb 1. x specification, and it can operate at f s and hs data rates. t he bit unst u f f er is a state machine, which str i ps a stuffed 0 b i t from the data stream and detects b i t stuff errors. in fs mod e bit stuff errors asser t s the rxerr signal. i n hs mode bit stuff erro rs are used to generate the eop signal so the rxerr signal is not asserted. 4.2.9 rx register rx register is in charge of convertin g serial d a ta received fro m the usb t o parallel data. 4.2.10 receive state machine the behavior of the receive state machine is described at chapter 6, function description. 4.2.11 nrzi encoder the nrzi encoder is compliant t o standard usb 1. x s pecification, and it can operate at fs and hs data rates. 4.2.12 bit stuffer bit stuffer is used by insert a zer o after every six consecutive ones in the data stream before the data is nrzi encoded in order to ensure adequ ate signal transition s . bit stuffing is enabled beginning wit h the sync pattern an d through the entire transmission. the data ?o ne? that ends the sync pattern is counted as the first one in a sequence. in fs mode bit stuffing by the transmitter is always enforced, without exception. if required by the bit stuffing rules, a zero bit is inserted even after the last bit before the tx vld signal is negated. after 8 bits are stuffed into the usb data stream t x rdy is negated for one byt e time to hold up the data stream on the data bus. 4.2.13 tx register tx register is in charg e of reading parallel dat a from the parallel app lication bu s interface upon command and serializing for transmission over usb. 4.2.14 transmit state machine the behavior of the transmit state machine is described at chapter 6, function description. ?2 00 0 - 2 0 0 1 g e nesy s l o gi c i n c.? a l l ri ght s rese rve d . page 8 of 23
gl 80 0 u sb - usb 2 . 0 utm i com p l i a n t tra n sce i v e r 5. pinning information 5.1 pin assignment usb 2.0 transceiver GL800USB u1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 fspeed hrst# hsterm# suspnd# rpu avdd0 dpf dph dmf dmh agnd0 rref avdd1 xo xi agnd1 test0 opmod1 opmod0 rxactv rxerr rxvld clkout txvld validh txrdy d0 d1 d2 d3 dvdd0 dgnd0 d4 d5 d6 d7 d8 d9 d10 d11 dvdd1 dgnd1 d12 d13 d14 d15 linest1 linest0 ?2 00 0 - 2 0 0 1 g e nesy s l o gi c i n c.? a l l ri ght s rese rve d . page 9 of 23
gl 80 0 u sb - usb 2 . 0 utm i com p l i a n t tra n sce i v e r 5.2 pin description pin # name i/o pull up/dow n description 1 fspeed i u p t r ansceiver select. this signal se lect s between the fs and hs transceivers: 0: high s peed transceiver enabled 1: full s peed transceiver enabled 2 hrst# i u p reset. chip reset input, active low . this signal is used to r e set all st ate machines in th e GL800USB. 3 hsterm# i u p t e rminatio n select . hs termination ena ble, active low 4 suspnd# i d o w n suspend mode enable, active low . this sig nal places the GL800USB in a mo de that draws minimal po wer from supplies. sh ut s down all blocks not necessar y for suspend/resume operation. while susp ended, hsterm# mu st always be disabled (fs mode) to ensure that the 1.5k pull-up on dp remains powered. 5 rpu - 3.3v pull up control for dpf 6 a v cc0 p positive analog supply (3.3v) 7 dpf b positive usb dif f erential dat a (full s peed) 8 dph b positive usb dif f erential dat a (high s peed) 9 dmf b negative usb dif f erential dat a (full s peed) 10 dmh b negative usb dif f erential dat a (high s peed) 11 agnd0 p analog ground (0v) 12 rref - 510ohm reference resistor input 13 a v cc1 p positive analog supply (3.3v) 14 xo b cryst a l o u t p u t 15 xi i 12mhz cryst a l/oscillator input 16 agnd1 p analog ground (0v) 17 test0 i down t e st mode enable 18 opmod1 i u p 19 opmod0 i d o w n operational mode. these signals select between various operational modes: [1] [0] des c r iption 0 0 0: normal operation 0 1 1: non-driving 1 0 2: disable bit s t uf fing and nrzi encoding 1 1 3: reserved ?2 00 0 - 2 0 0 1 g e nesy s l o gi c i n c.? a l l ri ght s rese rve d . page 10 of 23
gl 80 0 u sb - usb 2 . 0 utm i com p l i a n t tra n sce i v e r pin # name i/o pull up/dow n description 20 rxactv o receive active , active high. indicates that t h e receive st ate machine has detecte d sync an d is active. rxactv is negated af ter a bit s t uf f error or an eop is detected. in hs mode , rx actv must be ne gated no less than 3 and no more t han 8 clk s af ter an i d le st ate is dete c ted on the usb. and rxactv mus t be negate d for at least 1 clk between consecutive received p a cket s . in fs/fs only modes, rxactv mus t be negated no more th an 2 clks af ter a fs idle st ate is detected on the usb. and rx actv must be negated for at least 4 c l ks betwee n conse c utive receiv ed p a cket s . 21 rxerr o receive error , active high. 0: indicates no error . 1: indicates that a rece ive error has been detected. this output is clocked with the same timing as the dat a lines and can occur at anytime during a transfer . if asserted, it will force th e negation of rx vld on the next rising edge of clkout . 22 rxvld o receive dat a v a lid , active high. indicates that the dat a bus has valid dat a. the rx register is full and ready to be unloaded. the sie is expected to latch the dat a bus on the clock edge. 23 clkout o clock. this 30mhz clock ou tpu t is used for clocking re ceive and transmit hs/fs 16-bit p a rallel dat a. 24 txvld i t r ansmit v a lid , active high. ind i cates that t h e dat a bus is valid. the assertion of t r ansmit v a lid initiate s sync on the usb. the negation of t r ansmit v a lid initiates eop on the usb. in hs mode , the sync p a ttern must be asserte d on the usb between 8 and 16 bit times af ter th e assertion of txvld is detected by the t r ansmit s t ate machine. in fs/ fs only modes, the sync p a ttern must be asserted on the usb no less tha n 1 clk and no more than 5 clks af ter the assert io n of tx vld is detected by the t r ansmit s t ate machine. 25 v a lidh b t r ansmit/receive v a lid high , active high. ?2 00 0 - 2 0 0 1 g e nesy s l o gi c i n c.? a l l ri ght s rese rve d . page 1 1 of 23
gl 80 0 u sb - usb 2 . 0 utm i com p l i a n t tra n sce i v e r pin # name i/o pull up/dow n description 26 txrdy o t r ansmit dat a read y , active high. if tx vld is asserted, t he sie must always have dat a available for clocking in to the tx register on t he rising edge of clkout . if tx vld is true a n d txrdy is asserted at th e rising edg e of clkout , the GL800USB will load the dat a on the dat a b u s into the tx register on the next rising edge of clkout , at that time, sie should immediately present the dat a for next transfer on the dat a bu s. if tx vl d is asserted an d txrdy is negated, th e sie must hold the previo usly asserte d dat a on th e dat a bus. from the t i me t x vld is negate d , tx rdy is a don?t care for the sie. 27 d 0 b dat a bus 0 28 d 1 b dat a bus 1 29 d 2 b dat a bus 2 30 d 3 b dat a bus 3 31 dvcc0 p positive digit a l supply (3.3v) 32 dgnd0 p digit a l ground (0v) 33 d 4 b dat a bus 4 34 d 5 b dat a bus 5 35 d 6 b dat a bus 6 36 d 7 b dat a bus 7 37 d 8 b dat a bus 8 38 d 9 b dat a bus 9 39 d 10 b dat a bus 10 40 d 1 1 b dat a bus 1 1 41 dvcc1 p positive digit a l supply (3.3v) 42 dgnd1 p digit a l ground (0v) 43 d 12 b dat a bus 12 44 d 13 b dat a bus 13 45 d 14 b dat a bus 14 46 d 15 b dat a bus 15 ?2 00 0 - 2 0 0 1 g e nesy s l o gi c i n c.? a l l ri ght s rese rve d . page 12 of 23
gl 80 0 u sb - usb 2 . 0 utm i com p l i a n t tra n sce i v e r pin # name i/o pull up/dow n description 47 linest1 o 48 linest0 o line s t ate. these sign a l s refle c t the current st at e of the single ende d receiver s. they are combinatorial until a ?usable? clkout is available then they are synchronize d to clkout . they directly reflect the current st ate of the dp (lines t a te[0]) and dm (lines t a te[1]) signals: dm dp description 0 1 0 : s e 0 0 1 1: ?j? s t ate 1 0 2: ?k? s t ate 1 1 3 : s e 1 ?2 00 0 - 2 0 0 1 g e nesy s l o gi c i n c.? a l l ri ght s rese rve d . page 13 of 23
gl 80 0 u sb - usb 2 . 0 utm i com p l i a n t tra n sce i v e r 6. functional description 6.1 transmit operation 6.1.1 t r ansmit s t ate diagram reset !txrdy tx w a it send sync tx dat a load txrdy tx dat a w a it !txrdy send eop !txrdy h r s t # ! h r s t # txvld !txvld tx hold reg empty tx hold reg full tx hold reg empty tx hold reg full eop not done !txvld t r ansmit must be asserted to enable any transmissions. the sie assert s tx vld to begin a transmission. the sie negates tx vld to end a transmission. af ter the sie assert s tx vld it can assume that the transmission has st arted when it detect s tx rdy asserted. the sie assumes that the utm has consumed a dat a byte if tx rdy and tx vld are asserted. the sie must have valid p a cket information (pid) asserted on the dat a bus coincident with the assertion of tx vld. depending on the utm implement ation, tx rdy may be asserted by the t r ansmit s t ate machine as soon as one clk af ter the assertion of tx vld. tx vld and tx rdy are sampled on the rising edge of clkout . the t r ansmit s t ate machine does not automatically generate packet id? s (pids) or ?2 00 0 - 2 0 0 1 g e nesy s l o gi c i n c.? a l l ri ght s rese rve d . page 14 of 23
gl 80 0 u sb - usb 2 . 0 utm i com p l i a n t tra n sce i v e r crc. when transmitting, the sie is always expected to present a pid as the first byte of the dat a stream and if appropriate, crc as the last bytes of the dat a stream. 6.1.2 t r ansmit t i ming for dat a packet d a t a d a t a d a t a d a t a crc crc pid s yn c pid d a t a d a t a d a t a d a t a c r c c c r c c e o p p clkout txvld dat a txrdy dp/dm the sie negates tx vld to complete a p a cket. once negated, the t r ansmit s t ate machine will never reassert tx rdy until af ter the eop has been loaded into the t r ansmit shif t register . note that the utm t r ansmit s t ate machine can be ready to st art another p a ckage immediately , however the sie must confirm to the minimum inter-p acket delays identified in the usb 2.0 s pecification. 6.2 receive operation 6.2.1 receive s t ate diagram ?2 00 0 - 2 0 0 1 g e nesy s l o gi c i n c.? a l l ri ght s rese rve d . page 15 of 23
gl 80 0 u sb - usb 2 . 0 utm i com p l i a n t tra n sce i v e r reset !rxactv !rxvld rx w a it t r ip sync rxactv rx dat a rxvld rx dat a w a it !rxvld s t rip eop !rxactv !rxvld hrst# !hrst# sync detected dat a !dat a !sync idle st ate !dat a dat a abort 1 !rxactv !rxvld !rxerr t e rminate !rxactv abort 2 !rxvld !rxerr !idle st ate error rxerr eop detected receiv e error dat a sync 6.2.2 receive t i ming for dat a packet (w ith crc-16) ?2 00 0 - 2 0 0 1 g e nesy s l o gi c i n c.? a l l ri ght s rese rve d . page 16 of 23
gl 80 0 u sb - usb 2 . 0 utm i com p l i a n t tra n sce i v e r dat a dat a dat a dat a crc crc pid sy nc pid dat a dat a dat a dat a crc crc eo p dp/dm rxerr rxvld dat a rxactv clkout note that the usb 2.0 transceiver does not decode packet id? s (pids). they are p a ssed to the sie for decoding. this timing example is in hs mode. when a hs/fs utm is in fs mode there are approximately 40 clock cycles every byte ti me. the receive s t ate machine assumes that the sie captures the dat a on the dat a bus if rx actv and rx vld are asserted. in fs mode, rx vld will only be asserted for one clock per byte time. note that the receive and transmit sections of the transceiver operate independently . the receiver will receive any p a cket s on the u sb. the transceiver does not identify whether the p a cket that it is receiving from the up stream or the downstream port. the sie must ignore receive dat a while it is transmitting. ?2 00 0 - 2 0 0 1 g e nesy s l o gi c i n c.? a l l ri ght s rese rve d . page 17 of 23
gl 80 0 u sb - usb 2 . 0 utm i com p l i a n t tra n sce i v e r 7. electrical characteristics 7.1 absolute maximum ratings sy m b o l d e s c r i p t i o n m i n m a x vcc dc supply volt age -0.5v +3.6v v i dc input volt age -0.5v vcc+0.5v v i/o dc input volt age range for i/o -0.5v vcc+0.5v v ai/o dc input volt age for usb d+/d- pins -0.5v vcc+0.5v v i/oz dc volt age applied to output s in high z st ate -0.5v vcc+0.5v v esd s t atic discharge volt age 4000v t a a m b i e n t t e m p e r a t u r e 0 o c 1 0 0 o c 7.2 dc characteristics (digital pins) sy m b o l d e s c r i p t i o n min t y p m a x u n i t p d power dissip a t i o n m a v dd power supply v o lt age 3 3.3 3.6 v i o dc outp u t sink cu rre nt exclu d ing d+/d-/vcc/gnd 8 m a v il low level input volt age 0.9 v v ih high level input volt age 2.0 v v tl h low to high threshold volt age 1.3 1.43 1.56 v v th l high to low threshold volt age 1.3 1.43 1.56 v v hy s h y s t e r e s i s volt a g e - 0 - v v ol low level output volt age when i ol = 8 m a 0 . 4 v v oh high level output volt age when i oh = 8 m a 2 . 4 v i olk lea kag e cu rrent for p a ds with internal pull up or pull down resistor 4 6 a r dn pad internal pull down resister ( note 1 ) 7 9 k 105k 1 5 2 k o h m s r up pad internal pull up resister ( note 2 ) 7 8 k 104k 1 4 6 k o h m s ?2 00 0 - 2 0 0 1 g e nesy s l o gi c i n c.? a l l ri ght s rese rve d . page 18 of 23
gl 80 0 u sb - usb 2 . 0 utm i com p l i a n t tra n sce i v e r 7.3 dc characteristics (d+/d-) sy m b o l d e s c r i p t i o n min t y p m a x u n i t v ol d+/d- st atic output low (r l of 1.5k to 3.6v ) 0.3 v v oh d+/d- st atic output high (r l of 15k to gnd ) 2 .8 3.6 v v di dif f erential input sensitivity 0.2 v v cm dif f erential common mode range 0.8 2.5 v v se single-ended receiver threshold 0.2 v c in t r ansceiver cap a cit a n c e 2 0 p f i lo hi-z st ate dat a line leakage -10 +10 a z dr v driver output resist ance 28 43 ohms 7.4 sw itching characteristics sy m b o l d e s c r i p t i o n m i n t y p m a x u n i t f x1 x1 cryst a l frequency 1 1 .97 12 12.03 mhz t cy c x1 cycle time 83.3 ns t x1l x1 clock low time 0.45t cy c n s t x1h x1 clock high time 0.45t cy c n s t r30p f output p ad rise time from 10% to 90% swing with 30pf loading n s t f30p f output p ad fa ll time from 1 0 % to 90% swin g with 30pf loading n s t r50p f output p ad rise time from 10% to 90% swing with 50pf loading n s t f50p f output p ad fa ll time from 1 0 % to 90% swin g with 50pf loading n s t rusb d+/d- rise time with 50pf loading 4 20 ns t fusb d+/d- fall time with 50pf loading 4 20 ns ?2 00 0 - 2 0 0 1 g e nesy s l o gi c i n c.? a l l ri ght s rese rve d . page 19 of 23
gl 80 0 u sb - usb 2 . 0 utm i com p l i a n t tra n sce i v e r 7.5 timing chart 7.5.1 clkout rising and falling edge vs. input / output signals t2 t3 clkout output ( * ) input (**) t1 * output signals includes tx rdy , rx actv , rx err, rx vld, linest[1:0], d[15:0] ** input signals includes tx vld, v a lidh m a x m i n u n i t t 1 8 n s t 2 3 n s t 3 8 n s ?2 00 0 - 2 0 0 1 g e nesy s l o gi c i n c.? a l l ri ght s rese rve d . page 20 of 23
gl 80 0 u sb - usb 2 . 0 utm i com p l i a n t tra n sce i v e r 7.5.2 relationship betw een mode change and other input signals clkout hst e rm / opmod[1:0] / fspeed txvld / v a lidh t4 t5 t m a x m i n t 5 4 t t 6 4 t ?2 00 0 - 2 0 0 1 g e nesy s l o gi c i n c.? a l l ri ght s rese rve d . page 21 of 23
gl 80 0 u sb - usb 2 . 0 utm i com p l i a n t tra n sce i v e r 8. package dimension dimension (mm) dimension (mil) sy mbo l m i n . n o m . m a x . m i n . n o m . m a x . a 1 . 6 0 6 3 a 1 0 . 0 5 0 . 1 5 2 6 a 2 1 . 3 5 1 . 4 0 1 . 4 5 5 3 5 5 5 7 b 0 . 1 7 0 . 2 2 0 . 2 7 7 9 1 1 b 1 0 . 1 7 0 . 2 0 0 . 2 3 7 8 1 2 c 0 . 0 9 0 . 2 0 4 8 c 1 0 . 0 9 0 . 1 6 4 6 d 9.00 bsc 354 bsc d1 7.00 bsc 276 bsc e 9.00 bsc 354 bsc e1 7.00 bsc 276 bsc e 0.50 bsc 20 bsc l 0 . 4 5 0 . 6 0 0 . 7 5 1 8 2 4 3 0 l1 1.00 ref 39 ref r 1 0 . 0 8 3 r 2 0 . 0 8 0 . 2 0 3 8 y 0 . 0 7 5 3 0 3 . 5 7 0 3 . 5 7 1 0 0 2 1 1 1 2 1 3 1 1 1 2 1 3 3 1 1 1 2 1 3 1 1 1 2 1 3 note: 1. r e fer t o jed e c m s - 026 / bbc . 2 . dime ns ion d1 a nd e 1 do not incl ude mol d p r ot rus ion. a l l o w a b l e p r ot rus ion is 0 . 2 5 m m p e r s i de d1 a nd e 1 a r e ma ximum p l a s t ic b o dy s i ze dime ns ion incl uding mol d mis m a t ch. 3 . dime ns ion b doe s not incl ude da mb a r p r ot rus ion. a l l o w a b l e da mb a r p r ot rus ion s h a l l not ca us e t h e l e a d w i dt h t o ex c eed t h e m a x i m u m b d i m e n s ion by m o r e t h an 0.08mm. 4. all d i m e n s ion s in m i llim et er s. ?2 00 0 - 2 0 0 1 g e nesy s l o gi c i n c.? a l l ri ght s rese rve d . page 22 of 23
gl 80 0 u sb - usb 2 . 0 utm i com p l i a n t tra n sce i v e r 9. revision history v e r s i o n d e s c r i p t i o n d a t e 1 . 0 first d r a f t 2001/05/30 1.1 1. added function description of transmitting and receiving operations of utmi transceiver . 2. added electrical characteristics including timing chart. 3. eliminated application circuit for dif f erent publication. 2001/08/02 ?2 00 0 - 2 0 0 1 g e nesy s l o gi c i n c.? a l l ri ght s rese rve d . page 23 of 23

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